1. Field of Invention
The present invention relates to an output stage for high voltage tolerance electronic circuits. More particularly, the present invention relates to an output stage for a high voltage tolerance electronic circuit, the output stage having a protection device that protects against undesired starting up, and includes an output buffer made up of a complementary pair of transistors having a P-channel MOS pull-up transistor and an N-channel MOS pull-down transistor with these transistors being connected mutually to form an output terminal of the stage.
2. Discussion of the Related Art
As known to those skilled in the art, some electronic devices integrated on semiconductor and supplied with low supply voltage, e.g., 3 V, must sometimes be interconnected with other electronic devices operating with higher supply voltages, e.g., 5 V.
There are some problems in the use and management of resources common to both types of devices. For example, problems occur when a data bus is shared by different digital systems incorporating electronic circuits operating at 3 V and electronic circuits operating at 5 V.
In digital systems of this type there is normally present a logical control unit, e.g., a CPU (Central Processing Unit), which emits enable and disable signals for the various circuits sharing the data bus.
Specifically each circuit has control inputs and has a final output stage incorporating an output buffer made up essentially of a complementary pair of pull-up and pull-down circuits connected to the data bus. When a given circuit has to use the data bus, the CPU acts on the OE# (Output Enable) or CE (Chip Enable) signal inputs of the unused circuits to force the corresponding output buffers into an off state, or a "tristate."
A diagram of this situation is shown in FIG. 1 illustrating a group of electronic circuits sharing the same data bus even though operating with different supply voltages.
FIG. 1 also shows the bias voltages applied to the various output buffers when one of the circuits (in the example, the one with high power supply) is using the data bus.
From FIG. 1 it can be seen that each pull-up transistor of an output buffer that is turned off has its gate terminal and body terminal powered by a voltage Vcc of 3 V.
When the high power device (5 V) is operative the voltage on the data bus cannot reach the high logical level, i.e., 5 V, but is blocked at a Vcc value (3V)+min [.vertline.Vthp.vertline., V.gamma.], where Vthp is the threshold voltage of a PMOS transistor, and V.gamma. drain-bulk voltage drop.
In the case where .vertline.Vthp.vertline.&lt;V.gamma., the PMOS transistor is turned on. Otherwise, the NMOS transistors is turned on.
This involves an undesired consumption by the active device, which is forced to power the currents 11 and 12.
FIG. 2 shows an enlarged vertical cross section of the internal structure of a P-channel MOS transistor provided in an N well. The symbols S, G and D indicate respectively the terminals of the source, gate and drain regions.
B indicates the body or bulk terminal of the transistor.
A conventional solution consists of providing a diode connected in parallel to the P-channel pull-up transistor of the output buffer. This diode is directly biased like the drain-bulk junction but turns on first because of an expected lower threshold voltage.
Other circuit solutions of known type do not protect the drain-bulk junction without causing consumption of the circuit. These meet the High Voltage Tolerance specification but consume current during stand-by operation.